The present invention relates generally to semiconductor fabrication and more specifically to formation of devices having different channel lengths/critical dimension (CD) bias.
Applying different logic operations in different patterns is the current approach for system-on-chip (SOC) applications to achieve different poly critical dimension (CD) biases between after-etch inspection (AEI) CD and drawing CD (the layout dimension) within the wafer which are required for multiple devices to achieve both high performance and low leakage devices within the wafer.
U.S. Pat. No. 6,191,044 B1 to Yu et al. describes hard mask trimming.
U.S. Pat. No. 6,013,570 to Yu et al. describes a gate trim process.
U.S. Pat. No. 5,834,817 to Satoh et al. describes another gate trim process.
U.S. Pat. No. 6,110,785 to Spikes, Jr. et al. describes a gate trim etch process.
Accordingly, it is an object of one or more embodiments of the present invention to provide a method of achieving different critical dimension (CD) bias within a wafer for SOC application.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.